A small tool to view real-world ActivityPub objects as JSON! Enter a URL
or username from Mastodon or a similar service below, and we'll send a
request with
the right
Accept
header
to the server to view the underlying object.
{
"@context": [
"https://www.w3.org/ns/activitystreams",
{
"ostatus": "http://ostatus.org#",
"atomUri": "ostatus:atomUri",
"inReplyToAtomUri": "ostatus:inReplyToAtomUri",
"conversation": "ostatus:conversation",
"sensitive": "as:sensitive",
"toot": "http://joinmastodon.org/ns#",
"votersCount": "toot:votersCount"
}
],
"id": "https://mastodon.luca-alloatti.eu/users/luca/statuses/113486900912001410",
"type": "Note",
"summary": null,
"inReplyTo": "https://fedi.keinpfusch.net/users/uriel/statuses/01JCQNDV4AD1D5QM11MZYRCCXK",
"published": "2024-11-15T12:11:22Z",
"url": "https://mastodon.luca-alloatti.eu/@luca/113486900912001410",
"attributedTo": "https://mastodon.luca-alloatti.eu/users/luca",
"to": [
"https://mastodon.luca-alloatti.eu/users/luca/followers"
],
"cc": [
"https://www.w3.org/ns/activitystreams#Public",
"https://fedi.keinpfusch.net/users/uriel"
],
"sensitive": false,
"atomUri": "https://mastodon.luca-alloatti.eu/users/luca/statuses/113486900912001410",
"inReplyToAtomUri": "https://fedi.keinpfusch.net/users/uriel/statuses/01JCQNDV4AD1D5QM11MZYRCCXK",
"conversation": "tag:mastodon.luca-alloatti.eu,2024-11-15:objectId=132076:objectType=Conversation",
"content": "<p><span class=\"h-card\" translate=\"no\"><a href=\"https://fedi.keinpfusch.net/@uriel\" class=\"u-url mention\">@<span>uriel</span></a></span> E` vero, ma purtroppo quasi tutti i chips RISC-V sono chiusi (closed-source) e proprietari (è segreto non solo il layout, ma spesso anche l’HDL). Per i microprocessori una Instruction Set Architecture (ISA) aperta è soltanto una condizione necessaria ma non sufficiente per chips aperti e sicuri e purtroppo le novità sono rare. Forse la più recente è qui:<br /><a href=\"https://wiki.f-si.org/index.php?title=Moving_toward_VexiiRiscv\" target=\"_blank\" rel=\"nofollow noopener noreferrer\" translate=\"no\"><span class=\"invisible\">https://</span><span class=\"ellipsis\">wiki.f-si.org/index.php?title=</span><span class=\"invisible\">Moving_toward_VexiiRiscv</span></a></p>",
"contentMap": {
"it": "<p><span class=\"h-card\" translate=\"no\"><a href=\"https://fedi.keinpfusch.net/@uriel\" class=\"u-url mention\">@<span>uriel</span></a></span> E` vero, ma purtroppo quasi tutti i chips RISC-V sono chiusi (closed-source) e proprietari (è segreto non solo il layout, ma spesso anche l’HDL). Per i microprocessori una Instruction Set Architecture (ISA) aperta è soltanto una condizione necessaria ma non sufficiente per chips aperti e sicuri e purtroppo le novità sono rare. Forse la più recente è qui:<br /><a href=\"https://wiki.f-si.org/index.php?title=Moving_toward_VexiiRiscv\" target=\"_blank\" rel=\"nofollow noopener noreferrer\" translate=\"no\"><span class=\"invisible\">https://</span><span class=\"ellipsis\">wiki.f-si.org/index.php?title=</span><span class=\"invisible\">Moving_toward_VexiiRiscv</span></a></p>"
},
"attachment": [],
"tag": [
{
"type": "Mention",
"href": "https://fedi.keinpfusch.net/users/uriel",
"name": "@uriel@fedi.keinpfusch.net"
}
],
"replies": {
"id": "https://mastodon.luca-alloatti.eu/users/luca/statuses/113486900912001410/replies",
"type": "Collection",
"first": {
"type": "CollectionPage",
"next": "https://mastodon.luca-alloatti.eu/users/luca/statuses/113486900912001410/replies?only_other_accounts=true&page=true",
"partOf": "https://mastodon.luca-alloatti.eu/users/luca/statuses/113486900912001410/replies",
"items": []
}
}
}