A small tool to view real-world ActivityPub objects as JSON! Enter a URL
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Accept
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to the server to view the underlying object.
{
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"https://www.w3.org/ns/activitystreams",
{
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"inReplyToAtomUri": "ostatus:inReplyToAtomUri",
"conversation": "ostatus:conversation",
"sensitive": "as:sensitive",
"toot": "http://joinmastodon.org/ns#",
"votersCount": "toot:votersCount"
}
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"id": "https://fosstodon.org/users/mole99/statuses/114337479166197616",
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"published": "2025-04-14T17:24:36Z",
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"content": "<p>🧠 So what does it do? It is part RISC-V SoC and part eFPGA.</p><p>At its heart is the CV32E40X from the OpenHW group (<a href=\"https://github.com/openhwgroup/cv32e40x\" target=\"_blank\" rel=\"nofollow noopener noreferrer\" translate=\"no\"><span class=\"invisible\">https://</span><span class=\"ellipsis\">github.com/openhwgroup/cv32e40</span><span class=\"invisible\">x</span></a>) and an FPGA fabric generated using the FABulous framework (<a href=\"https://github.com/FPGA-Research/FABulous\" target=\"_blank\" rel=\"nofollow noopener noreferrer\" translate=\"no\"><span class=\"invisible\">https://</span><span class=\"ellipsis\">github.com/FPGA-Research/FABul</span><span class=\"invisible\">ous</span></a>).</p><p>While the SoC is fairly basic with a QSPI Flash and PSRAM controller, 8kB of SRAM and a UART, more functionality can be implemented using the embedded FPGA.</p>",
"contentMap": {
"en": "<p>🧠 So what does it do? It is part RISC-V SoC and part eFPGA.</p><p>At its heart is the CV32E40X from the OpenHW group (<a href=\"https://github.com/openhwgroup/cv32e40x\" target=\"_blank\" rel=\"nofollow noopener noreferrer\" translate=\"no\"><span class=\"invisible\">https://</span><span class=\"ellipsis\">github.com/openhwgroup/cv32e40</span><span class=\"invisible\">x</span></a>) and an FPGA fabric generated using the FABulous framework (<a href=\"https://github.com/FPGA-Research/FABulous\" target=\"_blank\" rel=\"nofollow noopener noreferrer\" translate=\"no\"><span class=\"invisible\">https://</span><span class=\"ellipsis\">github.com/FPGA-Research/FABul</span><span class=\"invisible\">ous</span></a>).</p><p>While the SoC is fairly basic with a QSPI Flash and PSRAM controller, 8kB of SRAM and a UART, more functionality can be implemented using the embedded FPGA.</p>"
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